chapter1-AppendixA-m2-ziavras

Ziavras simdvector processing 2 over the years

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Unformatted text preview: FPU. 128-bit: IEEE 754 quadruple-precision Some material is adapted from D. Culler & D. Patterson (UCB) (binary128) S. Ziavras SIMD/Vector Processing • • Status reg.: contains # of elements per vector reg. Many elements are loaded simultaneously (low-order memory interleaving): interleaving): Bank 0 bits Example 0 16 Address in module k 1 2 Module in bank 4 3 1-bank example example 2^k words per module Some material is adapted from D. Culler & D. Patterson (UCB) 14 15 31 S. Ziavras SIMD/Vector Processing (2) • Over the years traditional vector computers added – Strided addressing (skip elements) A A+m Access only elements with address A+n*m address A+n*m A+2m Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras SIMD/Vector Processing (3) – Gather/scatter addressing (indices of elements to access are stored in another vector register) Gather Indices of vector elements elements Scatter Vector Some material is adapted from D. Culler & D. Patterson (UCB) Vector Unit Ziavras S. SIMD/Vector Processing (4) • • Vector units in processors can be mainly...
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