chapter1-AppendixA-m2-ziavras

Chapter1-AppendixA-m2-ziavras

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Unformatted text preview: defined interfaces that are carefully implemented and thoroughly checked S. Ziavras Some material is adapted from D. Culler & D. Patterson (UCB) 1) 1) Taking Advantage of Parallelism • Increasing throughput of server computer via multiple processors or multiple disks • Detailed HW design – Carry lookahead adders uses parallelism to speed up computing sums from linear to logarithmic in number of bits per operand – Multiple memory banks searched in parallel in set-associative caches • Pipelining: overlap instruction execution to reduce the total time to complete an instruction sequence. – Not every instruction depends on immediate predecessor ⇒ executing instructions completely/partially in parallel possible – Classic 5-stage pipeline: 1) Instruction Fetch (Ifetch), 2) 2) Register Read (Reg), 3) Execute (ALU), 4) Data Memory Access (Dmem), S. Ziavras 5) Register Write (Reg) Some material is adapted from D. Culler & D. Patterson (UCB) Pipelined Instruction Execution Time (cl...
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This document was uploaded on 02/09/2014.

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