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chapter1-AppendixA-m2-ziavras

G mmu cache advanced pipelining etc mmu cache

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Unformatted text preview: owerPC, SPARC, Precision Architecture. SPARC Embedded: ARM, Hitachi SH, Thumb) JUSTIFICATION OF RISC DESIGNS – Program tracing (~1980): only 25% of CISC instructions are used 95% of the time [LOAD [LOAD,STORE,ADD, JUMP] JUMP] CISC may waste processor real estate » use real estate for more important “functions” (e (e.g., MMU, cache, advanced pipelining, etc.) MMU cache advanced etc » Hardwired implementations have better performance than microcoded ones Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras Typical RISC in 1980 Typical RISC in 1980’s • • • • • • • • < 100 instructions Fixed instruction formats 3-5 simple addressing modes Most instructions are register-based Memory access done only by load/store instructions Large register file (>32 registers) Hardwired control Higher clock rate Higher MIPS * rate • Lower CPI ** RISC instructions RISC instructions * MIPS: Million Instructions Per Second (a performance metric) ** CPI: clock Cycles Per Instruction Some material is adapted from D. Culler &...
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