chapter1-AppendixA-m2-ziavras

G dot product vector load vector store unary vector

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Unformatted text preview: taken advantage of in hand coding advantage of in hand coding Short, architecture-limited vectors with few regs. & simple memory addressing modes Difficult to use vectorizing compiler technology These SIMD instrs. are commonly found only in hand-coded libraries Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras Vector Instructions Register-Register Vector Operations V1•V2 → V3 S1•V1 → V2 V1•V2 → S1 M(1:n) → V1 V1 → M(1:n) V1 → V2 V1 → S1 binary vector scaling binary reduction (e.g., dot product) vector load vector store unary vector unary reduction Recently used in media processors Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras Vector Instructions (2) Vector Instructions (2) Memory-Memory Vector Operations M1(1:n) • M2(1:n) → M(1:n) S1• M1(1:n) → M2(1:n) M1(1:n) → M2(1:n) M1(1:n)• M2(1:n) → M (k) Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras DSPs Media Processors DSPs & Media Processors • Primarily for embedded applications • Real-time performance • Often deal with infinite, continuous streams of data • Frequently-used kernels in these applications often identified & specialized hardware is designed for their most efficient implementation • ISAs include QUIRKS that can imp...
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This document was uploaded on 02/09/2014.

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