chapter3-m6-ziavras

Ziavras ideal processor no artificial constraints

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Unformatted text preview: e – IBM Power2: can speculate on 2 branches per cycle S. Ziavras Ideal Processor • • • • • • • No artificial constraints on ILP Only limitations: imposed by actual data flows Register renaming: Infinite # of virtual regs. Perfect branch & jump prediction Memory address alias analysis: All memory addresses are known exactly & a L can be moved before a S provided that the EAs are not identical provided that the EAs are not identical Unlimited # of instrs. can be issued 1 cycle FU latencies, including Ls & Ss S. Ziavras Average ILP Available in Ideal Processor In...
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This document was uploaded on 02/09/2014.

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