Available for renaming il both the fp gp regs are

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: P regs. – In addition to 32 integer & 32 FP architectural registers • Next figure shows the effect of reducing the # of regs. available for renaming il – Both the FP & GP regs. are increased by # of regs. shown on the axis or in the legend regs. shown on the axis or in the legend S. Ziavras Effect of Finite Numbers of Registers Available for Renaming S. Ziavras More Realistic Assumptions • Up to 64 instructions issued per cycle Up to10 times the issue width of current processors • Tournament predictor: 1K entries • 16-entry return predictor • Perfect memory disambiguation memory disambiguation • Register renaming with additional virtual registers – 64 integer registers – 64 FP registers S. Ziavras Limits to ILP HW Model comparison Ideal Model IBM Power5 Instructions Issued per Issued per clock Infinite 4 Instruction Window Size Infinite 200 Renaming Registers Infinite 48 integer + 40 F...
View Full Document

This document was uploaded on 02/09/2014.

Ask a homework question - tutors are online