chapter3-m5-ziavras

Using this code segment same as for fig 34 show what

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ge) • Instr. other than store or branch with incorrect prediction incorrect prediction (NORMAL COMMIT) COMMIT • When instr. reaches head of ROB & its result is present in buffer • Update reg. with result • Remove instr. from ROB • Store: similar but memory is updated • Branch with incorrect prediction (speculation was wrong) • Flush ROB • Restart execution at correct successor of branch S. Ziavras Example Assume same latencies for FPUs as in earlier examples: “+” is 2 clock cycles, “*” is 10, & “/” is 40. Using this code segment (same as for Fig. 3.4), show what the status tables look like when MUL is ready to go to commit tables look like when MUL.D is ready to go to commit L.D L.D MUL.D F6,34(R2) F2,45(R3) F0,F2,F4 SUB.D DIV.D ADD.D F8,F6,F2 F10,F0,F6 F6,F8,F2 Although SUB.D completes execution, it does not commit until MUL.D commits (see next tables) commit until MUL.D commits (see next tables) S. Ziavras Example (2) • The reservation stations & register status field fi contain the same basic information that they did for Tomasulo’s algorithm. • Differences: RS #s are replaced with ROB entry #s Diff RS ROB in the Qj & Qk fields, as well as in the register status fields, & we have added the Dest field to the RS RS s • The Dest field designates the ROB # that is the destination for the result produced by this RS entry This example illustrates the key important difference example illustrates the key important difference between a processor with speculation & a processor with dynamic scheduling S. Ziavras Reservation Stations Name Busy Op Vj Vk Qj Qk Dest A Q Load1 No Load2 No Add1 No Add2 No Add3 No Mult1 No MUL.D Mem[45 Regs[F4] #3 +Regs[ R3]] Mult2 Yes DIV.D #3 Mem[34+Regs #5 [R2]] When MUL.D is ready to commit, only the L.Ds have MUL th committed; several others have completed execution S. Ziavras Reorder Buffer Entry Busy Instruction State 1 No L.D F6,34(R2) Commit 2 No L.D F2,45(R3) Commit 3 Yes 4 Yes 5 Yes MUL.D F0,F2,F4 Write result SUB.D F8,F6,F2 Write result DIV.D F10,F0,F...
View Full Document

This document was uploaded on 02/09/2014.

Ask a homework question - tutors are online