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Ziavras hw based speculation 3 1 2 separate result

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Unformatted text preview: low execution (execute operations as soon as operands become available) Approach here: extend Tomasulo’s algorithm (without loss here extend Tomasulo algorithm (without loss of generality, only FPU is studied) Examples: PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4 Alpha 21264 AMD K5/K6/Athlon Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon S. Ziavras HW-Based Speculation (3) 1. 2. Separate result bypassing from actual instr. completion allows instr. to execute & bypass results without instr to execute bypass results without permitting any updates that cannot be undone (until it’s known that instr. is no longer speculative) Include additional step: instruction commit additional step instr commit * When instr. Is no longer speculative, it’s allowed to update the reg. file or memory BASIC IDEA: Instrs. execute out-of-order but commit in order execute out commit in order Needs reorder buffer (ROB) to hold results of instrs. that have finished execution but have not committed S. Ziavras HW-Based Speculation (4) • ROB is a source of operands for instrs. just as RSs are in Tomasulo’s algorithm • Each ROB entry contains 4 fields ROB entry fields – Instr. type: indicates if instr. is branch (& has no destination result), store (has memory address destination), reg. operation (ALU operation or load, which has reg. destinations) – Destination field: reg. # (for loads & ALU operations) field reg loads ALU operations) or memory address (for stores) where instr. result must be written – Value field: holds value of instr. result until commits – Ready field: indicates whether instr. has completed S. Ziavras Basic Structure of MIPS FPU: Tomasulo’s Algorithm & Speculations ROB has replaced store buffers CDB can be made wider for Ziavras S. multiple completions/cycle Figure - Explanation • • • • Although the renaming function of RSs is replaced by the ROB, we still need a place to buffer operations (& operands...
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