chapter3-m5-ziavras

Ziavras integrated instruction fetch units separate

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Unformatted text preview: for buffer update & 1 wasted) No T 2 (1 cycle for buffer update & 1 wasted) No NT 0 Assume: MIPS-like & only taken branches stored in buffer S. Ziavras Integrated Instruction Fetch Units • • Separate autonomous unit feeding instrs. to the rest of the pipeline not just a single IF stage in the pipeline Functionality of integrated instr. fetch unit 1. Integrated branch prediction 2. Instr. prefetch prefetch 3. Instr. memory access & buffering/caching An ever increasing need to increase # of instrs. fetched per clock cycle per clock cycle new design ideas are always needed design ideas are always needed S. Ziavras Return Address Predictors • Predict an indirect jump (destination address unknown at static time) • Most correspond to procedure returns (other cases: case statements, FORTRAN-computed gotos, etc.) • Implementation for procedure returns – Small stack to cache/store the most recent stack cache/store the most recent return addresses • Push address on the stack at a call • Pop address at a return • For a large cache, the return addresses can be predicted be predicted with very high accuracy high acc S. Ziavras Prediction Accuracy for Return Address Buffer Operated as Stack Operated as a Stack SPEC benchmarks On average, returns account for 81% of indirect jumps in average returns account for 81% of indirect jumps in these benchmarks S. Ziavras Further Improvements • • Typical prediction accuracy from predictors already discussed: 80-95% Further improvement: reduce misprediction improvement reduce misprediction penalty – Fetch from both the predicted & unpredicted locations. For example, it requires: 1. Dual-ported memory 2. Interleaved cache 3. Fetch from one path & then from the other 4. Caching addresses from multiple paths in addresses from multiple paths in the target buffer S. Ziavras Multiple-Issue Processors • • Preceding techniques: eliminate data & control stalls to achieve ideal CPI of stalls to...
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