chapter3-m5-ziavras

Based on branch prediction s ziavras example assume

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Unformatted text preview: ly scheduled pipeline? pipeline? • IBM 360/91 – Static prediction – Instrs. are fetched & issued – Instrs. not actually executed until the branch has completed 1. IBM approach here 2. Later, speculation: improves by actually speculation improves by actually executing instrs. based on branch prediction • S. Ziavras Example • Assume: processor can issue any 2 instrs. if there are RSs of right type available • Extend Tomasulo’s alg. for integer & FP FUs (can be Tomasulo alg for integer FP FUs (can be used concurrently even if dependent) & regs., for MIPS LOOP: L.D ADD.D S.D DADDIU BNE F0,0(R1) ;F0=array element F4,F0,F2 ;add scalar in F2 F4,0(R1) ;store result R1,R1,#-8 ;decrement pointer (DW) pointer (DW) R1,R2,LOOP;branch R1!=R2 • Assume – 1 integer FU for ALU operations & EA calculations – Separate pipelined FPU for each operation type pipelined FPU for each operation type S. Ziavras Example (2) Issue & Write Results: each consumes 1 cycle Write Results: each consumes cycle Separate unit to evaluate branch predictions 2 CDBs CDBs No delayed branches, perfect branch prediction • Latency cycles between source instr. & instr. consuming its result – Integer ALU operations: 1 cycle – Load: 2 cycles – FP add: 3 cycles – – – – S. Ziavras Dual-Issue Example: Tomasulo’s Algorithm S. Ziavras Example (2) Resource usage S. Ziavras Single HW-Based Speculation While exploiting ILP, maintaining control dependences becomes an increasing burden • Just predicting branches may not be enough for a processor with a large ILP • Such a processor may need to execute a branch/cycle processor may need to execute branch/cycle 1. SPECULATE ON OUTCOME OF BRANCH 2. EXECUTE PROGRAM ASSUMING CORRECT PREDICTION – Dynamic scheduling just fetches & issues instrs. – Speculation techniques • HW-based (here) • Compiler-based • S. Ziavras HW-Based Speculation (2) • Combines 3 key ideas id 1. Dynamic branch prediction 2. Speculation to allow execution of instrs. before allow execution of instrs. before control dependences are resolved • Ability to undo effects of an incorrectly speculated sequence is absolutely essential speculated sequence is absolutely essential 3. Dynamic scheduling data-f...
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This document was uploaded on 02/09/2014.

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