{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

chapter3-m5-ziavras

chapter3-m5-ziavras - ECE 690 NJIT Computer Systems...

Info icon This preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 690 - NJIT Computer Systems Architecture Chapter 3 - Module 5 Instruction-Level Parallelism (ILP) & Its Exploitation Prof Sotirios G Ziavras Prof. Sotirios G. Ziavras S. Ziavras © Copyright
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Static Multiple Issue: VLIW Processors Instr. stream is explicitly organized by compiler to avoid dependences Simpler HW & very good compiler Early VLIWs were quite rigid in their instr. formats & effectively required recompilation of programs for different versions of the HW 2 nd generation of VLIW processors More flexible Compiler still has to do most of the work of finding & scheduling instrs. for parallel execution Pursued for desktop & server markets S. Ziavras
Image of page 2