chapter3-m5-ziavras

# In the loop twice ld muld from the 1st iteration have

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Unformatted text preview: 6 Execute F10 6 Yes ADD.D F6,F8,F2 Write result lt S. Ziavras DestiValue nation F6 Mem[34+Regs [R2]] F2 Mem[45+Regs [R3]] F0 #2xRegs[F4] F8 #1- #2 F10 F6 #4 + #2 FP Register Status Field Reorder # Busy F0 F1 F2 F3 F4 3 Yes F5 F6 F7 6 No No No No S. Ziavras No Yes F8 F10 4 … 5 Yes Yes Example Consider the code example used earlier for Tomasulo’s algorithm in execution Loop: L.D MUL.D S.D DADDIU BNE F0,0(R1) F4,F0,F2 F4,0(R1) R1,R1,#-8 R1,R2,Loop ;branches if R1≠R2 if R1 Assume: we have issued all the instrs. in the loop twice, & L.D & MUL.D from the 1st iteration have committed & all other instrs. have completed execution Normally, the store would wait in the ROB for both the EA operand (R1 here) & the value (F4 here). Since we are only considering the FP pipeline, assume the EA for the store is computed by Sthe time the instr. is issued . Ziavras Reorder Buffer En. Busy Instruction State 1 No L.D F0,0(R1) Commit 2 3 4 5 6 7 8 9 10 No MUL.D Yes S.D F4,F0,F2 Commit F4,0(R1) Write res. (WR) Yes DADDIU R1,R1,#-8 WR Yes BNE R1,R2,Loop WR R1 Yes L.D F0,0(R1) WR Yes MUL.D F4,F0,F2 WR F4 Yes S.D F4,0(R1) WR Yes DADDIU R1,R1,#-8 WR R1,R1,# Yes BNE R1,R2,Loop WR S. Ziavras Dest. F0 Value Mem[0+Regs [R1]] F4 0+Regs [R1] R1 #1xRegs[F2] #2 Regs[R1]-8 F0 F4 0+#4 R1 Mem[#4] #6xRegs[F2] #7 #4-8 FP Register Status Field Reorder # Busy F0 F1 F2 F3 F6 F7 F8 Yes No No No Yes No No … No 6 F4 F5 7 • Only the L.D & MUL.D instrs. have committed, although all the others have completed execution No RSs are busy & none are shown • The remaining instrs. will be committed as fast as possible • The first two reorder buffers are empty, but are shown fi for completeness S. Ziavras...
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## This document was uploaded on 02/09/2014.

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