chapter3-m4-ziavras

2 small special cache accessed with instr address

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: anch Prediction Buffer Implementation 1. 2. Small, special cache accessed with instr. address during IF phase Pair of bits (2-bit predictor) attached to each bl block in instr. cache and fetched with instr. S. Ziavras FP bench. are loop intensive 2-Bit Prediction Statistics • 2-bit prediction buffer • 4096 entries in buffer entries in buffer INTEG. BENCH. Higher branch frequencies branch frequencies SPEC89 Benchmarks, IBM Power, optimized code S. Ziavras 2-Bit Prediction Statistics (2) 4096-entry buffer vs. infinite buffer buffer vs infinite buffer S. Ziavras Correlating Branch Predictors Improve the prediction accuracy by also looking at the recent behavior of other branches (rather th than just the branch for which you’re trying to th predict) If (aa==2) aa=0; If (bb==2) bb=0; If (aa!=bb) { From SPEC92 benchmark eqntott (worst case for 2-bit predictor) predictor S. Ziavras Correlating (2-Level) Branch Predictors MIPS code to implement the previous code fragment code to implement the previous code fragment Assume: R1 aa & R2 bb DSUBUI R3,R1,#2 BNEZ R3,L1 ; branch b1 (aa!=2) DADD R1,R0,R0 ; aa=0 L1: DSUBUI R3,R2,#2 BNEZ R3,L2 ; branch b2 (bb!=2) DADD R2,R0,R0 ; bb=0 L2: DSUBU R3,R1,R2 ; R3=aa-bb BEQZ R3,L3 ; branch b3 (aa==bb) b3 Behavior of b3 is correlated with those of b1 & b2 • If both b1 & b2 are both not taken b3 will be taken S. Ziavras (m,n) Correlating Branch Predictor • Uses the behavior of the last m branches to choose from 2m n-bit branch predictors – Each n-bit predictor serves a single branch predictor serves single branch • Simple HW implementation – The global history of the m most recent global history of the most recent branches can be stored in an m-bit shift reg. – A branch-prediction buffer can be indexed by concatenating low-order bits from the branch bit th address with the m-bit global history S. Ziavras (2,2) Branch-Prediction Buffer LS bits 2^6=64 entries entries Buffer drawn as 2-D drawn as for simplicity Can be implemented as 2-bit be implemented as wide linear memory array Indexing: concatenate global h...
View Full Document

Ask a homework question - tutors are online