chapter3-m4-ziavras

Ziavras loadstore order of execution 2 to determine if

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Unformatted text preview: re Order of Execution (2) • To determine if a L can be executed at a given time, the if ti th processor can check whether any uncompleted S that precedes L in program order shares the same data memory address as memory address as L • S must wait until there are no unexecuted Ls or Ss that are earlier in program order & share the same data memory address memory address • To detect such hazards, the processor must have computed the data memory address associated with any earlier memory operation earlier memory operation – Simple solution: perform EA calculation in program order • Keep relative order between Ss & other relative order between Ss other memory references to same location • Ls can be reordered freely S. Ziavras Reducing Branch Costs With Dynamic HW Prediction • Simplest technique: branch-prediction buffer or branch history table – Small memory indexed by lower portion of address of branch instr. – Bit shows whether branch was taken last time shows whether branch was taken last time – Useful technique to reduce branch delay when longer than time to compute possible target PCs – Prediction may not be good because it may have been the result of another branch with similar lower address address This 1-bit prediction technique has limitations S. Ziavras Finite-State Machine for 2-bit Prediction Any 2-bit scheme: The prediction must miss twice before it’s changed S. Ziavras n-Bit Branch Predictors • • • • Use n-bit saturating counter (0 2n-1) Procedure 1. Increment counter on a taken branch on taken 2. Decrement counter on an untaken branch 3. If counter ≥ 2n-1, then predict branch as taken, otherwise (if counter < 2n-1) as untaken Doesn’t help with MIPS 5-stage pipeline (finds if help with MIPS pipeline (finds if branch is taken & the target address in ID stage). Suitable technique presented later 2-bit predictions do almost as well as n-bit predictors S. Ziavras Br...
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