chapter5-m2--ziavras

A1 excl a1 p2 value state 10 10 addr bus value action

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Unformatted text preview: 1: Read P2: Read A1 P2: P1 State Excl. Addr A1 Value 10 P2 State Addr Bus Value Action WrMs Proc. Addr P1 A1 Memory Value Addr Value P2: Write 20 to A1 P2: Write to A1 P2: Write 40 to A2 P2: Write to A2 Assumes A1 and A2 map to same cache block 44 Example step P1 Write 10 to P1:Write 10 to A1 P1: Read A1 P1: Read A1 P2: Read A1 P2: P1 State Addr Excl. A1 Excl. A1 P2 Value State 10 10 Addr Bus Value Action Proc. Addr WrMs P1 A1 Memory Value Addr Value P2: Write 20 to A1 P2: Write to A1 P2: Write 40 to A2 P2: Write to A2 Assumes A1 and A2 map to same cache block 45 Example step P1 Write 10 to P1:Write 10 to A1 P1: Read A1 P1: Read A1 P2: Read A1 P2: P1 State Addr Excl. A1 Excl. A1 Shar. A1 P2 Value State Addr 10 10 Shar. A1 10 Shar. A1 Bus Value Action Proc. Addr WrMs P1 A1 10 RdMs WrBk RdDa P2 P1 P2 A1 A1 A1 Memory Value Addr Value 10 10 A1 A1 10 10 P2: Write 20 to A1 P2: Write to A1 P2: Write 40 to A2 P2: Write to A2 Main memory sends copy to P2 Main memory gets a copy Assumes A1 and A2 map to same cache block 46 Example step P1 Write 10 to P1:Write 10 to A1 P1: Read A1 P1: Read A1 P2: Read A1 P2: P1 State Addr Excl. A1 Excl. A1 Shar. P2: Write 20 to A1 P2: Write to A1 P2: Write 40 to A2 P2: Write to A2 Inv. A1 P2 Value State Addr 10 10 Shar. A1 10 Shar. A1 Excl. A1 Bus Value Action Proc. Addr WrMs P1 A1 10 20 RdMs WrBk RdDa WrMs P2 P1 P2 P2 A1 A1 A1 A1 Memory Value Addr Value 10 10 A1 A1 A1 Assumes A1 and A2 map to same cache block 47 10 10 10 Example step P1:Wrrite 10 to A1 W it e 10 t A1 10 10 P1: Read A1A1 P1: Read P2: Read A1 P2: P1 State Excl. Excl. Value 10 10 Addr Bus Value Action WrMs M Proc. P1 Addr A1 RdMs WrBk RdDa WrMs WrMs WrBk P2 P1 P2 P2 P2 P2 A1 A1 A1 A1 A2 A1 Shar. Inv. A1 A1 10 20 Excl. A1 A1 Shar. Excl. Shar. P2: Write 20 to A1 P2: Write 20 to A1 Write Write A1 A1 P2: Write 40 to A2 A2 P2: Write Addr A1 A1 P2 State A2 40 10 Value 10 10 20 Memory Addr Value A1 A1 A1 A1 A1 Assumes A1 and A2 map to same cache block, but A1 !Ξ A2 48 10 10 10 10 20 And in Conclusion … • “End” of uniprocessors speedup => Multicores Parallelism challenges: % parallelizable, long latency challenges parallelizable long latency to remote memory • Centralized vs. distributed memory – Small MP vs. lower latency, larger BW for Larger MP MP lo latenc larger BW for Larger MP • Message Passing vs. Shared Address – Uniform access time vs. Non-uniform access time • Snooping cache over shared medium for smaller MP by invalidating other cached copies on write • Sharing cached data ⇒ Coherence (values returned by a read), Consistency (when a written value will be returned by a read) • Shared medium serializes writes ⇒ Write consistency 49...
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