chapter5-m2--ziavras

Coherence defines value returned by a read defines

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Unformatted text preview: • 100:34 Doesn’t show relation to original source/sequential program!! Too vague and simplistic; 2 issues 1. Coherence defines value returned by a read – defines read/write behavior to same location 2. Consistency determines when a written value will be returned by a read (by another processor) – defines behavior to other locations – Various models: e.g. SEQUENTIAL CONSISTENCY 21 (program result the same as executing on uniprocessor) Coherence & Consistency are Complementary • Coherence: defines the behavior of reads & writes to the sa same memory location – Value written by a processor can be read by other processors. – Writes to a location are seen in order. to location are seen in order – Does not say WHEN written values will be available. • Consistency: defines the behavior of reads & writes with respect to accesses to other memory locations (overall order of reads & writes) – writes to different locations will be seen in an order that will produce the correct program result (as per sequential execution of the entire program). sequential execution of the entire program). 22 Defining Coherent Memory System 1. Preserve Program Order: A read by processor P to location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P 2. Coherent view of memory: Read by a processor to location X that follows a write by another processor to X th returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses occur between the two accesses 3. Write serialization: 2 writes to same location by any 2 processors are seen in the same order by all processors – If not, a processor could keep value 1 since saw as last write cou sa as – For example, if the values 1 and then 2 are written to a location, processors can never read the value of the location as 2 and then later read it as 1 23 Write Consistency • For now assume 1. A write does not complete (and allow the next write does not complete (and allow the next write to occur) until all processors have seen the effect of that write 2. The processor does not change the order of any write with respect to any other memory access ⇒ if a processor writes location A followed by processor writes location followed by location B, any processor that sees the new value of B must also see the new value of A • These restrictions allow the processor to reorder Th th reads, but forces the processor to finish writes in program order 24 Basic Schemes for Enforcing Coherence • Program on multiple processors will normally have copies of the same data in several caches copies of the same data in several caches – Unlike I/O, where its rare • Rather than trying to avoid sharing in SW, SMP SMPs use a HW protocol to maintain coherent caches HW – Migr...
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This document was uploaded on 02/09/2014.

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