chapter5-m2--ziavras

Snoop every address placed on the bus 2 if a remote

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Unformatted text preview: 9 Locate up-to-date copy of data • • Write-through: get up-to-date copy from memory – Write through simpler if enough memory BW Write-back: harder; most frequent scheme – Most recent copy can be in a cache – Can use same snooping mechanism 1. Snoop every address placed on the bus 2. If a remote processor has dirty copy of requested cache block, it provides it in response to a read request and aborts the memory access » Complexity from retrieving cache block from a remote processor cache (it can take longer than retrieving it from shared memory) – Write-back needs lower memory bandwidth ⇒ Support larger numbers of faster processors 30 Cache Resources for WB Snooping • • • • Normal cache tags can be used for snooping Valid bit per block makes invalidation easy bit block invalidation Read misses easy since rely on snooping Writes ⇒ Need to know whether any other copies of the block are cached – No other copies ⇒ No need to place write on bus for WB – Other copies ⇒ Need to place invalidate on bus 31 Cache Resources for WB Snooping • To track whether a cache block is shared, add extra state bit (shared bit) associated with each cache block, like valid bit and dirty bit – Write to shared block ⇒ Need to place invalidate on bus and mark cache block as private (if an option) – No further invalidations will be sent for that block – This processor called owner of cache block – Owner then changes state from shared to th unshared (or exclusive ownership) 32 Cache behavior in response to bus • Every bus transaction checks the cache-address tags – Could interfere with processor cache accesses interfere with processor cache accesses • Reduce interference: duplicate tags in single cache/CPU – One set for local cache accesses; another set for bus set for local cache accesses; another set for bus accesses • Another way to reduce interference: use 2-level cache and L2 tags L2 – Since L2 less heavily used than L1 ⇒ Every entry in L1 cache must be present in the L2 entry in L1 cache must be present in the L2 cache, called the inclusion property – If Snoop gets a hit in L2 cache, then it arbitrates for th L1 the L1 cache to update the state and possibly retrieve th the data (usually requires a stall of the processor) 33 Example Protocol • Snooping coherence protocol is usually implemented by incorporating finite implemented by incorporating a finite-state controller (FSM) in each node • Logically, think of a separate controller associated with each cache block bl – That is, snooping operations or cache requests for different blocks can proceed independently • Implementations: a single controller allows multiple operations to distinct blocks to proceed in interleaved fashion – that is, one operation may be initiated before another is completed, even though only one cache access or one bus access is allowed at time 34 Write-through Invalidate...
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