chapter5-m2--ziavras

Write place write miss on bus write miss on bus

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Unformatted text preview: all caches to snoop bus Writes to clean blocks are treated as misses 38 Write-Back State Machine – CPU Request CPU Read hit • State machine for CPU requests for each each cache block • Non-resident blocks invalid Invalid CPU Read Place read miss on bus Shared (read/only) CPU Write Local CPU request Place Write Miss on bus Cache Block Block State CPU read hit CPU write hit write hit CPU Write Place Write Miss on Bus Write Miss on Bus Exclusive (read/write) CPU Write Miss (?) Write Miss (?) Write back cache block Place write miss on bus 39 Write-Back State Machine- Bus request • State machine for bus requests for each cache block Request reaching this processor via the bus Invalid Invalid Write miss for this block Write Back Block; (abort memory access) access) Exclusive (read/write) Write miss for this block this block Shared (read/only) Read miss for this block Write Back Back Block; (abort memory access) 40 Local Block State Machine CPU Read hit • State machine for CPU requests for each each cache block Initiated by remote CPU Invalid CPU Read Place read miss on bus Shared (read/only) CPU Write Place Write Miss on bus Cache Block Block State CPU Read miss CPU Read miss Write back block, Place read miss Place read miss on bus on bus CPU Write Place Write Miss on Bus Write Miss on Bus Exclusive CPU Read hit (read/write) CPU Write hit hit CPU Write Miss Write Miss Write back cache block Place write miss on bus 41 Write-back State Machine-III CPU Read hit • State machine for CPU requests eac for each cache block and for bus requests for each cache block block Cache State Write miss for this block Shared Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU read miss CPU Read miss for this block Write back block, Place read miss Write Back Place read miss on bus CPU Write Block; (abort on bus Place Write Miss on Bus memory access) access) Block Block Read miss miss Write Back Back Exclusive (read/write) CPU read hit read hit CPU write hit for this block Block; (abort memory access) CPU Write Miss Write Miss Write back cache block Place write miss on bus 42 Example (with 2 CPUs, P1 & P2) step P1 Write 10 to P1:Write 10 to A1 P1: Read A1 P1: Read A1 P2: Read A1 P2: P1 State Addr P2 Value State Addr Bus Value Action Proc. Addr Memory Value Addr Value P2: Write 20 to A1 P2: Write to A1 P2: Write 40 to A2 P2: Write to A2 Assumptions 1. A1 and A2 map to same cache block 2. Initial cache state: invalid 43 Example step P1 Write 10 to P1:Write 10 to A1 P1: Read A1A1 P...
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This document was uploaded on 02/09/2014.

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