Cache invalidate all other cache copies prwr buswr

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Unformatted text preview: Protocol PrRd/ -PrWr / BusWr • 2 states per block in each cache – as in uniprocessor V – state of a block is a p-vector* of states BusWr / - – Hardware state bits associated with blocks that are in the cache PrRd / BusRd – other blocks can be seen as being in I invalid (not-present) state in that cache • Writes invalidate all other cache invalidate all other cache copies PrWr / BusWr BusWr – can have multiple simultaneous readers State Tag of block of block,but write invalidates them write invalidates them PrRd: Processor Read PrWr: Processor Write BusRd: Bus Read Bus Read BusWr: Bus Write * p: processors. V or I for each processor Data State Tag Data P n P 1 $ Bus Mem $ I/O devices 35 Is 2-state Protocol Coherent? • Processor only observes state of memory system by issuing memory operations (1. PRESERVES PROGRAM ORDER PER PROCESSOR) PROCESSOR) • Assume bus transactions & memory operations are atomic and a one-level cache – all phases of one bus transaction complete before next one starts phases of one bus transaction complete before next one starts – processor waits for memory operation to complete before issuing next – with one-level cache, assume invalidations applied during bus transaction • All writes go to bus + atomicity – Writes serialized by order in which they appear on bus (bus order) => invalidations applied to caches in bus order (2. COHERENT VIEW OF MEMORY) • How to insert reads in this order? to insert reads in this order? – Important since processors see writes through reads, so determines whether write serialization is satisfied – But read hits may happen independently and do not appear on bus or enter directly in bus order enter directly in bus order • Let’s understand other ordering issues 36 Ordering (You need: 3. WRITE SERIALIZATION system) For a single location P0: R P1: R P2: • • R R R W R R R Coherent memory R R R R R R W R R Writes establish a partial order Doesn’t constrain ordering of reads, though shared-medium (bus) will order read misses too – any order among reads between writes is fine, as long as in program order NEEDED: 1. Coherent writes writes 2. Order all the writes according to the sequential 37 program order ( synchronize) Example: Write-Back Snoopy Protocol • Invalidation protocol, write-back cache • • • • – Snoops every address on bus – If it has a dirty copy of requested block, provides that block in response to the read request and aborts the memory access Each memory block is in one state – Clean in all caches and up-to-date in memory (Shared) – OR Dirty in exactly one cache (Exclusive) – OR Not in any caches Each cache block is in one state (cache conrollers track these) – Shared : block can be read block can be read – OR Exclusive : cache has only copy, its writeable, and dirty – OR Invalid : block contains no data (in uniprocessor cache too) Read misses: cause...
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This document was uploaded on 02/09/2014.

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