chapter5-m3-ziavras

impossible for both if statements l1 l2 to be true

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Unformatted text preview: lockit R2,R0,#1 R2,0(R1) R2,lockit ; load linked ; locked value ; branch if store fails • 1st branch: spinning loop • 2nd branch: resolves races when 2 processors see the lock available simultaneously il 50 Another MP Issue: Memory Consistency Models Memory Consistency Models • What is consistency? When must a processor see the new value? e.g., seems that new value? e.g., seems that P1: L1: • A = 0; ..... A = 1; if (B == 0) ... P2: L2: B = 0; ..... B = 1; if (A == 0) ... Impossible for both “if statements” L1 & L2 to be true? – What if write invalidate is delayed & processor continues? • Memory consistency models: what are the rules for such cases? • Sequential consistency (SC) model: – accesses of each processor are kept in order – accesses among processors are arbitrarily interleaved – delay all memory accesses until all invalidates done 51 Memory Consistency Model • Faster schemes exist than sequential consistency • Not an issue for most programs; they are synchronized – All accesses to shared data are ordered by synchronization operations accesses to shared data are ordered by synchronization operations write (x) {after “acquire (s)”} ... release (s) {unlock} ... acquire (s) {lock} ... read(x) • Only those programs willing to be nondeterministic are not synchronized; “data race” outcome is f(proc. speed) • Several Relaxed Models for Memory Consistency since Relaxed Models for Memory Consistency most programs are synchroni...
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