chapter5-m3-ziavras

if dirty bit on then recall line from dirty proc 20

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: turn p[i] ON; supply recalled data to i;} • Write to main memory by processor i: • If dirty-bit OFF then { supply data to i; send invalidations to all If di OFF caches that have the block; turn dirty-bit ON; turn p[i] ON; ... } • if dirty-bit ON then {recall line from dirty proc ……..} 20 • ADD a directory to each node in the DM MP (distributed-memory multiprocessor) to • Track caches that share addresses with this processor • Communicate with processor & memory • Over common bus, or • Separate port to memory, or • Be part of a central controller that monitors all transfers 21 Directory Protocol • Similar to Snoopy Protocol: 3 states – Shared: ≥ 1 processors have block data processors ha block data memory & all involved caches are up-to-date – Uncached (no processor has it; invalid in any cache) – Exclusive/modified/DIRTY: 1 processor (owner) has data; memory out-of-date • • In addition to cache state, must track which processors have data when in the shared state processors have data when in the shared state (usually bit vector, 1 if processor has copy) Keep it simple(r) 1. Writes to non-exclusive data => write miss 2. Processor blocks until access completes 3. Assume messages received and acted upon in order sent 22 Directory Protocol • No bus and don’t want to broadcast: – interconnect no longer single arbitration point no longer single arbitration point – all messages have explicit responses • Terms: typicall...
View Full Document

This document was uploaded on 02/09/2014.

Ask a homework question - tutors are online