chapter5-m3-ziavras

13 true sharing false false sharing compulsory

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Unformatted text preview: going from 1 MB to 8 MB (L3 cache) 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 1 MB 2 MB L3 4 MB 8 MB Cache size BETTER VIEWGRAPH! 13 True sharing & false false sharing: Compulsory Compulsory misses increase slightly increase going from 1 to 8 CPUs 14 MP Performance 2MB Cache Commercial Workload: OLTP, Decision Support (Database), Search Engine (D (Memory) Cycles per Instruction • True sharing, false sharing increase going from going from 1 to 8 CPUs 3 2.5 2 Instruction Conflict/Capacity Cold False Sharing True Sharing 1.5 1 0.5 0 1 2 4 Processor count 6 8 15 Misses/1000instrs. drop with increases in L3 block size L3 block size L3 16 A Cache Coherent System Must: • Provide set of states, state transition diagram, and actions actions • Manage coherence protocol – (0) Determine when to invoke coherence protocol – (a) Find info about state of block in other caches to determine action » whether need to communicate with other cached copies – (b) Locate the other copies Locate other copies – (c) Communicate with those copies (invalidate/update) • (0) is done the same way on all systems – state of the line is maintained in the cache – protocol is invoked if an “access fault” occurs on the line • Different protocols distinguished by (a) to (c) 17 Bus-based Coherence • All of (a), (b), (c) done through broadcast on bus – faulting processor sends out a “search” – others respond to the search probe and take necessary action • Could do it...
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This document was uploaded on 02/09/2014.

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