chapter5-m3-ziavras

False sharing v hit assume words x1 and x2 in same

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: lly shared Miss would not occur if block size were 1 word if bl 7 Example: True v. False Sharing v. Hit? Assume words x1 and x2 in same cache block (in shared state) in the caches of both P1 and P2 the caches of both P1 and P2 Time P1 1 Write x1 2 3 True, False, Hit? Why? True miss; invalidate x1 in P2 Read x2 False miss; x1 irrelevant to P2 miss; x1 irrelevant to P2 Write x1 4 5 P2 False miss; x1 irrelevant to P2* Write x2 False miss; x1 irrelevant to P2 x2 miss; x1 irrelevant to P2 Read x2 True miss; share x2 with P1 *: Write miss required for P1 to get exclusive access of block 8 System for Benchmarking • • • • 4-processor (Alpha 21164) SM system Results for either Alpha-Server 4100 or its simulator Alpha 21164 21164 – 300 MHz – Issues up to 4 instructions per clock cycle – 3-level cache » L1: 2 (distinct instr. & data) 8K direct-mapped on-chip caches • Block: 32 bytes • Data cache: write-through to L2 with write buffer » L2: 96 KB on-chip, unified 3-way set associative (7 cycles) • Block: 32 bytes • Write-back » L3: 2 MB off-chip, unified direct-mapped (21 cycles) MB off unified cycles • Block: 64 bytes • Write back – Main memory access time: 80 cycles (typical, no co...
View Full Document

This document was uploaded on 02/09/2014.

Ask a homework question - tutors are online