chapter5-m3-ziavras

Higher bandwidth 2 response is matched to request 3

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Unformatted text preview: rvene in the meantime Benefits 1. Higher bandwidth 2. Response is matched to request 3. Buffering between bus and cache controllers between bus and cache controllers operations overlap (faster than atomic) 4. Reduce serialization down to bus arbitration Reduce serialization down to bus arbitration 3 Limitations in Symmetric Shared-Memory Multiprocessors and Snooping Protocols Multiprocessors and Snooping Protocols • Bottleneck: single memory accommodates all CPUs ⇒ Multiple memory banks memory banks • For bus-based multiprocessor bus must support both coherence traffic & normal pp memory traffic ⇒ Multiple buses or interconnection networks (crossbar or small point-to-point) • AMD Opteron – Memory connected directly to each dual-core chip connected directly to each dual chip – Point-to-point connections for up to 4 chips – Remote memory and local memory latency are quite similar Opteron: like a UMA computer 4 Crossbar, multistage, etc. (ICN) UMA with an ICN rather than a bus 5 Cache Performance of Symmetric SharedMemory Multiproce...
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This document was uploaded on 02/09/2014.

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