chapter5-m3-ziavras

Its th it really time to get onboard the

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Unformatted text preview: dual core?) – CTO: "Intel is taking a conservative approach that focuses on single-thread performance. You won't see mediocre thread performance just for the sake of getting multiple cores on a die.” • CTO urged software companies to support multicore designs with software that can efficiently di divide tasks among multiple execution threads. "It's th "It' really time to get onboard the multithreaded train" 24 Assume for Simplicity (for Now) 1. Messages are received and acted upon in the order they order they’re sent sent – Not normally true in practice Complications Ensures that invalidates sent by a processor are honored before transmission of new messages 2. Serialization of writes & knowledge of completion of invalidates is not as simple as in snooping protocols snooping protocols • Requires explicit acknowledgments in response to write misses & invalidations 25 Possible Directory Protocol Messages Message type Source Destination Msg Content Read miss Local cache Home directory P, A – Processor P reads data at address A; make P a read sharer and request data Write miss miss Local cache cache Home directory directory P, A – Processor P has a write miss at address A; make P the exclusive owner and request data Invalidate Home direcrory Home direcrory Remote cache cache A – Invalidate a shared copy in a remote cache containing A Fetch Home directory Remote cache A – Fetch the block at address A and send it to its home...
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This document was uploaded on 02/09/2014.

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