chapter5-m3-ziavras

Problem exchange includes a write which invalidates

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Unformatted text preview: : try: ll daddui sc beqz R2,0(R1) R3,R2,#1 R3,0(R1) R3,try * Address stored in LINK REGISTER ; load linked ; increment R3 (R2)+1 ; store conditional store conditional ; store failed if R3=0 ; if R3=1 …… 48 User Level Synchronization— Operation Using this Primitive • Spin locks: processor continuously tries to acquire, spinning around a loop trying to get the lock lockit: li exch bnez R2,#1 R2,0(R1) R2,lockit ;atomic exchange with lock ;already locked? • Problem: exchange includes a write, which invalidates all other copies; this generates considerable bus traffic • Solution: start by simply repeatedly reading the variable; when it changes, then try exchange (“test and test&set”): lockit: LD R2,0(R1) ; load of lock ; not available spin BNEZ R2,lockit DADDUI R2,R0,#1 ; R2 (R0)+1 = 0+1 = 1 (MIPS) EXCH R2,0(R1) ; swap ; branch if lock wasn’t 0 BNEZ R2,lockit ; use the shared resource since lock is available 49 Even Better Lockit: LL BNEQZ DADDUI SC SC BEQZ R2,0(R1) R2,...
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This document was uploaded on 02/09/2014.

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