chapter5-m3-ziavras

Uniprocessor cache miss traffic 3 cs classification

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Unformatted text preview: ssors Multiprocessors Cache performance depends on 1. Uniprocessor cache miss traffic • 3 C’s classification • Capacity (blocks discarded and later retrieved) • Compulsory (very first block access) • Conflict (if not fully-associative cache) 2. Traffic caused by communication – Results in invalidations and subsequent cache misses » Coherence miss 4th C 6 Coherence Misses 1. True sharing misses arise from the communication of data through the cache coherence mechanism • Invalidates due to 1st write to shared block establishes ownership • Reads by another CPU of modified block in different by another CPU of modified block in different cache block is transferred Miss would still occur if block size were 1 word 2. False sharing misses when a block is invalidated bl because some word in the block, other than the one being read, is written into • Invalidation does not cause a new value to be does not cause new value to be communicated, but only causes an extra cache miss • Block is shared, but no word in block is actua...
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