chapter5-m3-ziavras

Wrms p1 excl a1 10 darp p1 excl a1 10 shar a1 rdms p2

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Unformatted text preview: rocessor 1 Processor 2 Interconnect step P1: Write 10 to A1 P1: Read A1 P2: Read A1 Directory Memory P1 P2 Bus Directory Memory State Addr Value State Addr Value Action Proc. Addr Value Addr State {Procs} Value A1 Ex {P1} WrMs P1 A1 Excl. A1 10 DaRp P1 A1 0 Excl. A1 10 P2: Write 20 to A1 P2: Write 40 to A2 A1 and A2 map to the same cache block 35 Example Processor 1 Processor 2 Interconnect step P1: Write 10 to A1 P1: Read A1 P2: Read A1 P1 P2 Bus State Addr Value State Addr Value Action Proc. WrMs P1 Excl. A1 10 DaRp P1 Excl. A1 10 Shar. A1 RdMs P2 Shar. A1 10 Ftch P1 Shar. A1 10 DaRp P2 Directory Memory Directory Memory Addr Value Addr State {Procs} Value A1 A1 Ex {P1} A1 0 A1 A1 A1 10 10 A1 A1 A1 Shar. {P1,P2} { P2: Write 20 to A1 P2: Write 40 to A2 10 10 10 10 10 Write Back A1 and A2 map to the same cache block 36 Example Processor 1 Processor 2 Interconnect step P1: Write 10 to A1 P1: Read A1 P2: Read A1 P2: Write 20 to A1 P1 P2 Bus State Addr Value State Addr Value Action Proc. WrMs P1 Excl. A1 10 DaRp P1 Excl. A1 10 Shar. A1 RdMs P2 Shar. A1 10 Ftch P1 Shar. A1 10 DaRp...
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