chapter5-m3-ziavras

Memory location and atomically increments it 0

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Unformatted text preview: Set register to 1 & swap register to swap – New value in register determines success in getting lock » 0 if you succeeded in setting the lock (you were first) » 1 if other processor had already claimed access if other processor had already claimed access – Exchange operation is indivisible • Test-and-set: tests a value and sets it if the value passes the test • Fetch-and-increment: it returns the value of a memory location and atomically increments it – 0 ⇒ synchronization variable is free 47 Uninterruptable Instruction to Fetch and Update Memory and Update Memory • Hard to have read & write in 1 instruction: use 2 instead • Load linked (or load locked) + store conditional linked load locked) store conditional – Load linked returns the initial value – Store conditional returns 1 if it succeeds (no other store to same memory location memory location* since preceding load) and 0 otherwise preceding load) and otherwise • Example doing atomic swap with LL & SC: try: mov ll sc beqz mov R3,R4 R2,0(R1) R3,0(R1) R3,try R4,R2 ; move exchange value R3 (R4) ; load linked R2 load linked R2 Mem(R1) ; store conditional Mem(R1) (R3) IF NONE ; branch store fails if R3 = 0 ; R4 (R2), if R3=1 • Example doing fetch & increment with LL & SC...
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This document was uploaded on 02/09/2014.

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