chapter5-m3-ziavras

Chapter5-m3-ziavras

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Unformatted text preview: CPU Read hit Fetch: send Data Write Back message to home directory CPU read miss: send Data read miss: Data Write Back message and read miss to home directory CPU write miss: write miss: send Data Write Back message and Write Miss to home directory 28 State Transition Diagram for Directory State Transition Diagram for Directory • • • • Same states & structure as the transition diagram th di for an individual cache block – Use UNCACHED state instead of Invalid 2 actions 1. update directory state & 2. send messages to satisfy requests Tracks all copies of memory block Also indicates an action that updates the sharing th th set, Sharers, as well as sending a message 29 Directory State Machine • State machine for Directory requests for each memory block • Uncached state state if in memory Uncached Data Write Back: Sh Sharers = {} {} (Write back block) Write Miss: Sharers = {P}; send Fetch/Invalidate; send Data Value Reply Data Value Reply msg to remote cache Read miss: Sharers = {P} send Data Value Reply Write Miss: Sharers = {P}; send Data Value Reply msg Exclusive (read/write) Read miss: Sharers += {P}; send Data Value Reply Shared (read only) Write Miss: send Invalidate to Sharers; to Sharers; then Sharers = {P}; send Data Value Reply msg Read miss: Sharers += {P}; send Fetch; send Data Value Reply msg to remo...
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This document was uploaded on 02/09/2014.

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