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Unformatted text preview: (The first printing of the 2nd edition left out the NOT. If you have a used book, it might have the error.) Note: For 3.8 assignment of B,C is interchangeable. 4. Chapter 3, problem 3.16. Generate a logic circuit for a PLA. 5. Chapter 3, problem 3.24. Design of an adder. 3.24 (a) X=0 => S = A+B, X=1 => S = A+C 3.24 (b) Circuit diagram is same as Figure 3.39 with the following modifications: C = NOT (B), Carryin = X 6. Chapter 3, problem 3.25. Estimating propagation delay in circuits. 3.25 (a) 3 gate delays 3.25 (b) 3 gate delays 3.25 (c) 3*4 = 12 gate delays 3.25 (d) 3*32 = 96 gate delays...
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 Spring '08
 CAVALLARO
 Boolean Algebra, Logic gate, The Circuit, Logical connective, Patt & Patel

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