CPE 151 quiz 1-8

1 answer incorrect correct answer 15 mark s for this

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Unformatted text preview: except : Choose one answer. a. Clock tree insertion b. Synthesis of the gate level netlist c. Place and route of the layout d. Creation of the RTL code e. None of these c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =26906 11/ 25/ 12 Correct Mark s for this s ubmis s ion: 2/2. His tory of Res pons es : # Action Response Time Raw score Grade 1 Grade Creation of the RTL code 10:41:36 on 25/11/12 2 2 2 Close&Grade Creation of the RTL code 10:41:43 on 25/11/12 2 2 “Clock trees” are used distribute clocks across a VLSI chip in order to reduce delay. Mark s : 3 0/2 Answer: True False Incorrect Mark s for this s ubmis s ion: 0/2. His tory of Res pons es : # Action Response Time Raw score Grade 1 Grade True 10:39:52 on 25/11/12 0 0 2 Close&Grade True 10:41:43 on 25/11/12 0 0 4 Crosstalk is typically neglected during timing analysis since it rarely causes errors. Mark s : 0/2 Answer: True False Incorrect Mark s for this s ubmis s ion: 0/2. His tory of Res pons es : # Action Response Time Raw score Grade 1 Grade True 10:39:42 on 25/11/12 0 0 2 Close&Grade True 10:41:43 on 25/11/12 0 0 A clock is routed to a flip- flop through a 826μm long wire which is found to h...
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This test prep was uploaded on 02/16/2014 for the course CPE 151 taught by Professor Heedley during the Fall '08 term at CSU Sacramento.

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