Unformatted text preview: ave a
delay of 22.6psec. If this same wire continues for another 325.5μm to connect to a
Mark s :
flop, what will be the clock skew between the two flip-
picoseconds? Neglect the input capacitance of the flip-
flops. 5 c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =26906 2/ 3 EEE 234/ C pE 151: Quiz 8 - VLSI c loc k ing Answer: 43.9 Incorrect
Correct answer: 3.5
Mark s for this s ubmis s ion: 0/2.
His tory of Res pons es :
# Action Response Time Raw score Grade 1 Grade 43.9 10:38:31 on 25/11/12 0 0 2 Close&Grade 43.9 10:41:43 on 25/11/12 0 0 Finis h review You are logged in as Juan Carlos Torres (Logout) EEE 234/CpE 151 c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =26906 3/ 3...
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