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Unformatted text preview: to use higher clock frequencies b. Reduced dependence on clock duty cycle c. Reduced data latency d. None of these e. Increased data throughput Correct
Mark s for this s ubmis s ion: 2/2. W ith previous penalties this gives 1/2.
His tory of Res pons es :
# Action Response Time Raw score Grade 1 Grade Reduced dependence on clock duty cycle 10:22:49 on 25/11/12 0 0 2 Grade Reduced data latency 10:22:52 on 25/11/12 2 1 10:23:01 on 25/11/12 2 1 3 Close&Grade Reduced data latency A VLSI designer plans to pipeline a data path using D-
flops with tclk-
50 psec, tsetup = 41 psec and thold = 45 psec. If a 996 MHz clock is used with a
Mark s :
maximum clock skew of 57.4 psec, and there are a maximum of 16 logic gates
flops, each having a gate delay of 30 psec, then what is the timing
margin for setup time...
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This test prep was uploaded on 02/16/2014 for the course CPE 151 taught by Professor Heedley during the Fall '08 term at CSU Sacramento.
- Fall '08