CPE 151 quiz 8

Mark s 3 02 answer true false incorrect mark s

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Unformatted text preview: lysis since it rarely causes errors. Mark s : 0/2 Answer: True False Incorrect Mark s for this s ubmis s ion: 0/2. His tory of Res pons es : # Action Response Time Raw score Grade 1 Grade True 10:39:42 on 25/11/12 0 0 2 Close&Grade True 10:41:43 on 25/11/12 0 0 A clock is routed to a flip- flop through a 826μm long wire which is found to have a delay of 22.6psec. If this same wire continues for another 325.5μm to connect to a Mark s : second flip- flop, what will be the clock skew between the two flip- flops in 0/2 picoseconds? Neglect the input capacitance of the flip- flops. 5 c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =26906 2/ 3 11/ 25/ 12 EEE 234/ C pE 151: Quiz 8 - VLSI c loc k ing Answer: 43.9 Incorrect Correct answer: 3.5 Mark s for this s ubmis s ion: 0/2. His tory of Res pons es : # Action Response Time Raw score Grade 1 Grade 43.9 10:38:31 on 25/11/12 0 0 2 Close&Grade 43.9 10:41:43 on 25/11/12 0 0 Finis h review You are logged in as Juan Carlos Torres (Logout) EEE 234/CpE 151 c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =26906 3/ 3...
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This test prep was uploaded on 02/16/2014 for the course CPE 151 taught by Professor Heedley during the Fall '08 term at CSU Sacramento.

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