CPE 151 quiz 9

A vlsi designer plans to pipeline a data path using

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Unformatted text preview: tup = 29 psec and thold = 44 psec. If a 816 MHz clock is used with 15 Mark s : logic gates between flip- flops, each having a gate delay of 27 psec, then what is the 2/2 maximum clock skew that can be tolerated in picoseconds? 1 Answer: 760.4 Correct Mark s for this s ubmis s ion: 2/2. His tory of Res pons es : # Action Raw score Grade 760.4 11:00:41 on 25/11/12 2 2 2 Close&Grade Mark s : 0/2 Time 1 Grade 2 Response 760.4 11:21:37 on 25/11/12 2 2 Which of the following can NOT cause a hold time violation? Choose one answer. a. Large clock skew b. Small flip- flop clk- to- Q delays c. Having too few logic gates between flip- flops c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =2690...
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This test prep was uploaded on 02/16/2014 for the course CPE 151 taught by Professor Heedley during the Fall '08 term at CSU Sacramento.

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