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Answer: True False Incorrect
Mark s for this s ubmis s ion: 0/2.
His tory of Res pons es :
# Action Response Time Raw score Grade 1 Grade True 11:21:34 on 25/11/12 0 0 2 Close&Grade True 11:21:37 on 25/11/12 0 0 c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =26908 2/ 3 11/ 25/ 12 EEE 234/ C pE 151: Quiz 8 - VLSI c loc k ing A clock is routed to a flip-
flop through a 127μm long wire which is found to have a
delay of 12.1psec. If this same wire continues for another 402.4μm to connect to a
Mark s :
flop, what will be the clock skew between the two flip-
picoseconds? Neglect the inpu...
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This test prep was uploaded on 02/16/2014 for the course CPE 151 taught by Professor Heedley during the Fall '08 term at CSU Sacramento.
- Fall '08