CPE 151 quiz 12

Mark s 3 02 answer true false incorrect mark s

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Unformatted text preview: ave a delay of 14.6psec. If this same wire continues for another 193.4μm to connect to a Mark s : second flip- flop, what will be the clock skew between the two flip- flops in 0/2 picoseconds? Neglect the input capacitance of the flip- flops. 4 Answer: Incorrect Correct answer: 1.4 Mark s for this s ubmis s ion: 0/2. c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =26923 2/ 3 11/ 25/ 12 EEE 234/ C pE 151: Quiz 8 - VLSI c loc k ing 5 Mark s : 2/2 Even carefully designed clock trees cannot completely eliminate clock skew on a chip. Answer: True False Correct Mark s for this s ubmis s ion: 2/2. His tory of Res pons es : # Action Response Time Raw score Grade 1 Grade True 11:30:47 on 25/11/12 2 2 2 Close&Grade True 11:30:50 on 25/11/12 2 2 Finis h review You are logged in as Juan Carlos Torres (Logout) EEE 234/CpE 151 c li. ec s . c s us . edu/ m od/ quiz/ rev iew. php?q=14&at t em pt =26923 3/ 3...
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