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Unformatted text preview: an “H” shape e. Inserted in a place & route block before other logic gates are
Mark s for this s ubmis s ion: 0/2.
His tory of Res pons es :
# Action Response Time Raw score Grade 1 Grade Laid out on a chip in an “H” s hape 11:32:49 on 25/11/12 0 0 11:32:56 on 25/11/12 0 0 2 Close&Grade Laid out on a chip in an “H” shape A VLSI designer plans to pipeline a data path using D-
flops with tclk-
42 psec, tsetup = 36 psec and thold = 46 psec. If a 1432 MHz clock is used with a
Mark s :
maximum clock skew of 91 psec, and there are a minimum of 3 logic gates
flops, each having a gate delay of 25 psec, then what is the timing
margin for hold time analysis in picoseconds? 3 Answer: Incorrect
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- Fall '08