The green regions in the image to the right have

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Unformatted text preview: the silicon in selected locations. The green regions in the image to the right have these implanted alien atoms. Copyright © 2011, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. Removing Photo Resist – scale: wafer level (~300mm / 12 inch) After the ion implantation the photo resist will be removed and the material that should have been doped (green) has alien atoms implanted now (notice slight variations in color) High-k Dielectric Deposition Applying High-k Dielectric – scale: wafer level (~300mm / 12 inch) Instead of a traditional insulator between a transistor’s gate and its channel, Intel applies multiple layers of High-K dielectric material to the surface of the wafer. This material is applied one atomic layer at a time (yellow in the image). This reduces electrical leakage and enables more energy-efficient processors. 7 Applying High-k dielectric – scale: wafer level (~300mm / 12 inch) There are multiple layers of individual molecule layers being applied to the surface of the wafer. The two yellow layers shown here represent two of these layers. High-k Dielectric – scale: transistor level (~50-200nm) This step shows how the High-k insulator has been applied to the whole wafer. The High-k material is thicker than the traditional Silicon-Dioxide layer while it has the same capacitive properties to maximize performance. Due to the increased thickness less current leaks through this innovative insulator. Copyright © 2011, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. Photo Lithography Applying Photo Resist – scale: wafer level (~300mm / 12 inch) The liquid (dark color here) that’s poured onto the wafer while it spins is a photo resist finish similar as the one known from film photography. The wafer spins during this step to allow very thin and even application of this photo resist layer. 8 Exposure – scale: wafer level (~300mm / 12 inch) The photo r...
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This note was uploaded on 02/16/2014 for the course EECS 40 taught by Professor Chang-hasnain during the Spring '08 term at University of California, Berkeley.

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