SandToSilicon32nm

These three holes will be filled with copper or other

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Unformatted text preview: e been etched into the insulation layer (red color) above the transistor. These three holes will be filled with copper or other material which will make up the connections to other transistors. 10 Electroplating – scale: transistor level (~50-200nm) The wafers are put into a copper sulphate solution at this stage. The copper ions are deposited onto the transistor thru a process called electroplating. The copper ions travel from the positive terminal (anode) to the negative terminal (cathode) which is represented by the wafer. After Electroplating – scale: transistor level (~50-200nm) On the wafer surface the copper ions settle as a thin layer of copper. Copyright © 2011, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. Metal Layers Polishing – scale: transistor level (~50-200nm) The excess material is polished off. 11 Metal Layers – scale: transistor level (six transistors combined ~500nm) Multiple metal layers are created to interconnect (think: wires) in between the various transistors. How these connections have to be “wired” is determined by the architecture and design teams that develop the functionality of the respective processor (e.g. Intel® Core™ i5 Processor ). While computer chips look extremely flat, they may actually have over 30 layers to form complex circuitry. If you look at a magnified view of a chip, you will see an intricate network of circuit lines and transistors that look like a futuristic, multi-layered highway system. Copyright © 2011, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. When wafer processing is complete, the wafers are transferred from the fab to an assembly/test facility. There, the individual die are first tested, then the they are singulated and the ones that passed their test are packaged. Finally, a thorough test of the packaged part is...
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This note was uploaded on 02/16/2014 for the course EECS 40 taught by Professor Chang-hasnain during the Spring '08 term at Berkeley.

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