ECE559_Fall2009_Exam1_Solution

0 4 n x o c v page 6 of 13 vdd vol 1 02

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Unformatted text preview: gly, if all the NMOS transistors are ON, i.e., A = B = C = 1 (as OFF current is assumed to be zero), the minimum value of R is achieved. R f o e u l a v m u m i n i m To calculate IAB we have to determine the voltage at the intermediate node, VX. Both the NMOSs with inputs A and B will be apparently in linear region. This is because of the reason that there is only 0.2 V to be dropped across both the transistors and for both of them the linear region condition would be satisfied, i.e., Vds,A < VGS,A - Vtn and Vds,B < VGS,B - Vtn. Anyway, we can double-check later on after finding the voltage VX. Since the NMOSs with inputs A and B are serially connected I AB = I A = I B 2 ( 0.2 − vx ) = 1.0 − 0.3 * vx − vx 2 ⇒ (1.0 − 0.3 − vx ) * ( 0.2 − vx ) − ( ) 2 2 2 ( 0.2 − vx ) = 0.7 * vx − vx 2 . ⇒ ( 0.7 − vx ) * ( 0.2 − vx ) − 2 2 Since, VX has to be less than 0.2 V and the transistor with input A is ON, we can neglect VX with respect to 0.7 V. Also, body effect is not considered here. Accordingly, 2 ( 0.2 − vx ) = 0.7 * vx − vx 2 0.7 * ( 0.2 − vx ) − 2 2 ⇒ 0.2 − vx = vx ⇒ vx = 0.1 We can verify now that both of the NMOSs are indeed in linear region. Page 7 of 13 Exam 1 ECE 559 (Fall 2009), Purdue University I R = I NMOS = I AB + I C = I B + I C 0.8 0.12 0.22 −6 ⇒ = 40 *10 4* 0.7 * 0.1 − + 1* 0.7 *0.2 − R 2 2 0.8 = 40 *10−6 ( 4* 0.065 + 1*0.12 ) R 0.8 ⇒ = 40 *10−6 * 0.38 R 0.8 ≃ 40 *10−6 *0.40 ⇒ R ⇒ R ≃ 5*104 Ω ⇒ So, Rminimum = 50 KΩ In the previous calculation we have assumed different VOL for different input vector combinations and calculated the minimum R. If VOL is assumed to be the output low voltage for all the possible input combinations, then we have to consider only the highest-resistance path from output to ground when the output is low because that will cause the highest VOL at the output. We need choose the minimum R for which the highest VOL will occur because if R is more than a minimum value, VOL will just go lower. Accordingly, we need to consider only IC because that corresponds to the lowest ON current through the NMOS network when the NMO...
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This note was uploaded on 02/19/2014 for the course ECE 559 taught by Professor Staff during the Fall '08 term at Purdue University.

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