Clearly show the applied clock signals e v i t a g e

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Unformatted text preview: v o i k o g c o l l c c i t o a t t s e g u d n i s n ) u o i t i d n c o - e c r a y n a s d i o v b t r a P a 1 [ C2MOS latches are inverting. In a pipelined datapath we can that we are getting inverted signals at the inputs of the latches that will be again inverted to get the noninverted inputs. To avoid race condition due to clock overlaps, we need to have logic functions between the latches. So we have to add one inverter stage in between the latches. We can design the subsequent stages depending on what logic function we have at the next stage or if it’s the primary output, we are done. : e i t r e v n - i n o s s n o i t u l o a n D D V D D V K L C A A A K L C B K B + L C A B K L A C D D V K K Page 3 of 9 n u L C B g m B L C S Exam 2 Solution ECE 559 (Fall 2009), Purdue University Implement NOR operation as a pipelined datapath using C2MOS latches that . Clearly draw all the transistors and the applied clock signals in your diagram. Write your assumptions, if any. c s s t n i o p 0 p a l i o g r e v l c o i m...
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