ECE559_Fall2009_Exam2_Solution

# Determine the set up time determine the propagation

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Unformatted text preview: ersity It needs explanation for VB, max = VDD - Vtn. When VA’ = |Vtp|, VB’ = 0, and CLK = VDD, at VB = VDD - Vtn, current stops flowing through the series-connected MOSs at stage 2, so VB remains at VDD - Vtn. a y l e d r e t r e n v i e n Setup time is the time for the nodes A’/B’ to be valid that is . o 1 e a g t s o t n g i d n o p s e r r o ) 4 e a g t s d n a 3 , e a g t s 2 , e a g t s o t g n i d n o p s e r r o c s y a l e d r e t r e v n i e e r h ) e a g t s o t n g i d n o p s e r r o c a y l e d r e t r e n v i e n a t s o t g n i d n o p s e r r o c y a l e d r e t r e v n i e n o n a h t s s e Page 6 of 9 g ) o To be specific, the hold time should be because it takes one inverter delay corresponding to stage 1 for D to change voltage levels at nodes A’ and B’. e c t After the rising edge of clock occurs, input D must be kept stable until the values at the nodes A and B get stable corresponding to the values we have at nodes A’ and B’. If D changes, the values at the nodes A’/B’ would change and that will in turn affect the node values at A and B. So the hold tim...
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## This note was uploaded on 02/19/2014 for the course ECE 559 taught by Professor Staff during the Fall '08 term at Purdue.

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