So we have to add one inverter stage in between the

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Unformatted text preview: cisely answer the following questions with explanation. Write your assumptions, if any. : s t n i o p 0 2 m e l b o r P 4 [ s t n i o p 0 What are the minimum and maximum voltages possible at the nodes A and B? Determine the set-up time. Determine the propagation delay. Determine the hold time. 1 [ t s t s t s n i o p 0 1 [ n i o p 0 1 [ n i o p 0 1 [ D 3 4 e g a t e g a t D ) a ) b ) ) c d V S 2 e a g S t 1 e a g S t S A A ’ K L C K L C Q D B B ’ : n o i t VA’, min = |Vtp|, VA’, max = VDD, VB’, min = 0, VB’, max = VDD. It needs explanation for VA’, min = |Vtp|. When D = VDD and CLK = 0, at VA’ = |Vtp|, current stops flowing through the series-connected MOSs at stage 1, so VA’ remains at |Vtp|. = t n V - D D V B x a m , V , 0 = = B n i m , V , D D V A x a m , V , 0 = A n i m , V Accordingly, . We have assumed that VA’, min = |Vtp| is low enough to have VA, max = VDD which normally is quite a good assumption. Page 5 of 9 u l o ) S a Exam 2 Solution ECE 559 (Fall 2009), Purdue Univ...
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This note was uploaded on 02/19/2014 for the course ECE 559 taught by Professor Staff during the Fall '08 term at Purdue.

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