Unformatted text preview: k c a o n l c d y o t n g e u i s d ) u n o i t i d n c o - e c a r y n a s d i o v c t r a P a 1 [ C2MOS latches are inverting. In a pipelined datapath we can
that we are
getting inverted signals at the inputs of the latches that will be again inverted to get the noninverted inputs. To avoid race condition due to clock overlaps, we need to have
logic functions between the latches. So we have to add one inverter stage in between the
latches. We can design the subsequent stages depending on what logic function we have at the
next stage or if it’s the primary output, we are done. For dynamic logic, we should make sure
that when the dynamic logic is evaluating, the latch that is followed-by is in transparent mode.
Charge loss due to cascading of the dynamic gates is assumed to be non-substantial.
: e i t r e v n - i n o s s n o i t u l o a n D
D D D V V
K L C A
K L C K L C A
K B + L C K A B
K L L C A C
K L C K L D V C
K Page 4 of 9 n u C B g m B L C S Exam 2 Solution ECE 559 (Fall 2009), Purdue University Consider the edge-triggered register shown below. Clearly and con...
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- Fall '08
- Logic gate, Purdue University