Unformatted text preview: n VDD VOUT I n+ p+ R p+ n+ W n+ p+ d n VIN d p Vss I n-well W R
b I p-substrate R
S S R I From this condition, derive the following inequality for the triggering of the latchup ( I dd − I RS ) p Page 1 of 2 n respectively. p βnpn are the common-emitter current gains for the and . n + 1) ( I RS + I RW β pnp ) p Where βpnp and npn n β npn β pnp (β
> 1+ transistors, Homework 1 ECE 559 (Fall 2009), Purdue University Prove that the minimum VDD for CMOS circuit operation is : ) s t m i L i S O M C ( 2 m e l b o r P VDD |min = 2 ln(2) KT
q Consider a pseudo-NMOS 2-input NAND gate as in the figure : ) S O M N - o u d e s P ( 3 m e l b o r P below. Use the foll...
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- Fall '08
- Transistor, Surface-mount technology, 2-input nand gate, CMOS circuit operation, common-emitter current gains