E to confirm your answer use l 300 nm vdd 25 v t p 5

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Unformatted text preview: e z r i o t m i s i n s i n m a r t e e h t t a f g o s D h N t A d N i w t m u p u n i m - 2 i t p a o r Find out the o f y a l e d n o : i 2 t a g m a e l p b o o r r p P Draw a layout of a 2-input NAND gate with the optimized widths that you have got for the problem 1. You can round the widths of the transistors as allowed by the technology library that you have used in lab. Perform DRC, extract layout, do layout vs. schematic check, and at last simulate your extracted netlist to verify its functionality. Submit the plots of schematic and layout of your design. Page 1 of 2 Homework 3 ECE 559 (Fall 2009), Purdue University : m 3 e l b o r P In the circuit given below, the input voltage, Vin varies as shown. Determine the energy dissipation when 1) RC >> T and 2) T >> RC, respectively. D D V R + C T n i n i V _ V Page 2 of 2...
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This note was uploaded on 02/19/2014 for the course ECE 559 taught by Professor Staff during the Fall '08 term at Purdue University-West Lafayette.

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