Use vdd 25v l 300n input signal period 10n with 50

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Unformatted text preview: e d a r t a s r o w m e g a r e v a - i t e : 2 m e l b o r P Consider a 2-input static CMOS based NAND gate and a NAND gate (precharge-evaluation based). Perform a SPICE simulation to calculate the dynamic power your results comparatively consumption for both. State your assumptions, if any and discussing if it meets your expectation or not. Use c i m a n y d i n a l p x e VDD = 2.5V, L = 300n, Wp = 900n, Wn = 450n (same Wp/Wn are also applicable for precharge/evaluate MOSs), Input/Clock signal period = 10n with 50% duty cycle, Rise/Fall time = 0.5n, Delay time = 1n, Signal probabilities: pA=1= 0.6, pB=1 = 0.6 (A is the input closer to the output). : 3 m e l b o r P Perform a DC analysis in SPICE for both an NMOS and a PMOS transistor to get their output characteristics (VDS vs. ID as a function of VGS). From these two characteristics, derive the corresponding CMOS inverter’s transfer characteristics and identify the regions of operation for each NMOS and PMOS along the input voltage range. Use VDD = 2.5V, VTH = VTH0, L = 300n, Wp = 900n, Wn = 450n. Page 1 of 1...
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This note was uploaded on 02/19/2014 for the course ECE 559 taught by Professor Staff during the Fall '08 term at Purdue.

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