{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

T c e r r o a t r a p c y n o i t a t i n f l a a n o

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: S and the widths of the output inverter MOSs that achieve the of the gate, however, you should of the gate. Clearly state your procedure and assumptions, if ensure the any. Use f n o i t a r e p o t s e t s a f y t i l a n o i t c n u t c e r r o c Rise/Fall Time = 0.01 ns, Delay Time = 0.01 ns, Clock Period = 200 ns (with 50% duty cycle), the high/low state of the other input signals you can choose at your convenience. Page 1 of 2 Homework 5 ECE 559 (Fall 2009), Purdue University ) c t r a P Decrease the threshold voltages of the NMOSs in the pull-down network. You can change the effective threshold voltages of the NMOSs by adding a battery at the inputs in addition to the input voltages applied so that gate-overdrive VGS - VT changes. You don’t need to change the threshold voltage in the library. Use battery voltage, VB = 0.8 V. Repeat Part b). You can consider breaking down the 16-inputs in multiple cascaded stages as necessary. Explain why or why not. Draw and submit your final schematic (on paper by hand is OK if you don’t use Cadence). Explain the differences in results with the Part b). Page 2 of 2...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online