Unformatted text preview: S and the widths of
the output inverter MOSs that achieve the
of the gate, however, you should
of the gate. Clearly state your procedure and assumptions, if
f n o i t a r e p o t s e t s a f y t i l a n o i t c n u t c e r r o c Rise/Fall Time = 0.01 ns, Delay Time = 0.01 ns, Clock Period = 200 ns (with 50% duty cycle), the
high/low state of the other input signals you can choose at your convenience. Page 1 of 2 Homework 5 ECE 559 (Fall 2009), Purdue University ) c t r a P Decrease the threshold voltages of the NMOSs in the pull-down network. You can
change the effective threshold voltages of the NMOSs by adding a battery at the inputs in
addition to the input voltages applied so that gate-overdrive VGS - VT changes. You don’t need to
change the threshold voltage in the library. Use battery voltage, VB = 0.8 V.
Repeat Part b). You can consider breaking down the 16-inputs in multiple cascaded stages as
necessary. Explain why or why not. Draw and submit your final schematic (on paper by hand is
OK if you don’t use Cadence). Explain the differences in results with the Part b). Page 2 of 2...
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